This invention relates to a digital signal processor. For example, the present invention relates to a technique which will be effective for use in a digital signal processor or the like having a product/sum calculation function necessary for accomplishing equivalently a digital filter.
A digital signal processor with built-in control ROM (Read-Only Memory), data ROM and data RAM (Random Access Memory) of a stored program system is known. When a transversal type digital filter is accomplished by such a digital signal processor, for example, the product/sum calculation such as represented by the flowchart of FIG. 10 must be repeatedly executed in every sampling period and the sampling data must be delayed by one sampling period for the next product/sum calculation.
A digital signal processor having the structure such as shown in FIG. 11 has been proposed in order to execute the product/sum calculation described above at a high speed. The sampling data Xi read from the RAM is applied to one of the input terminals of a multiplication circuit MULT. This data is placed on the Y-BUS when selected by a bus selection circuit SEL0. The filter coefficient Ci is read from the ROM and inputted to the other input terminal of the multiplication circuit MULT through an X-BUS. The result of the multiplication (product) is applied to one of the input terminals of an arithmetic and logic unit ALU. The output signal of an accumulator, which holds the result of the previous calculation (sum) of the arithmetic and logic unit, is applied to the other of the input terminals of the arithmetic and logic unit ALU. In this digital signal processor, the sampling data Xi and the filter coefficient Ci are inputted sequentially to the multiplication circuit and the product/sum calculation of the following equation which is necessary for the filter calculation and is shown in FIG. 10 can be accomplished at a high speed: ##EQU1##
Furthermore, a delay register DREG for holding the sampling data read from the RAM for one sampling period is disposed in this digital signal processor. After the read operation of the next sampling data Xi+1 is made, the sampling data Xi read from the RAM is written into its address "i+1". In this manner, the shift operation of the sampling data necessary for the next filter calculation is executed automatically without relying upon program control as shown in FIG. 10.
The digital signal processor having the product/sum calculation function and the sampling data shift function is described in, for example, "Hitachi Digital Signal Processor (HSP) HD61810 Users' Manual" published by Hitachi, Ltd., September, 1985.